Package technology is constantly improving in order to keep up with the advances in silicon technology. Multi layered packages exhibit several failure modes that can be predicted using modern software tools. This paper provides a methodology for creating a high-fidelity model of the interposer with all the conductor geometries in Abaqus/CAE. The two failure modes that are explored with this model are package warpage prediction due to actual copper imbalance and filled microvia delamination. Each layer can meshed based on the actual geometry in the layout design. Package warpage is caused by copper imbalance between the two sides of the interposer.
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