Synchronization is the cure to growing IC design complexity

 

Semiconductor Design teams are exposed to enormous pressures

They collaborate from different locations around the globe, they run parallel, complex projects producing large amounts of data and they need to produce ever more varied and customized designs. 

To cope with those pressures, they need a foundation of collaborative design and information systems easy to use, seamlessly tied together, scaling across distributed teams while supporting intellectual property (IP) reuse. 

Design Collaboration

Effectively master your Design Closure Complexities

Leading Semiconductor Companies benefits from using Silicon Thinking Collaborative Design solutions:

  • Efficient intellectual property (IP) management and reuse
  • Graphical analytics to manage design closure
  • Instant access to the latest design data for all design teams
  • End-to-end traceability, from requirements to verification and validation
  • Packaging reliability simulation and testing
  • Enhanced product variation and defect management
Semiconductor Design Data Management

The beauty of ENOVIA Pinpoint is that with a single click, you see a graphical representation of the path, with the green-dot to red-dot path indicating where you need to go [to address the glitch]. It’s as easy to use as Google Maps, as the tool zooms down to a single instance, which allows you to diagnose the particular problem. Then you can zoom all the way back out and map all of the failing paths and compare them to your layout.

Dwight Galbi Principle/Manager, Qualcomm

13 of the top 15 semiconductor companies around the world
are using Dassault Systèmes Collaborative Design solutions to boost design productivity

Pinpoint design issues before they become critical...

Semiconductor Collaborative Design

... and reduce:

  • Missed Deadlines

    Due to resources not being synchronized or having to correct avoidable problems Excessive Design

  • Re-Spins and Waivers

    Due to wrong data being handed off for tape-out or late changes being introduced without review

  • High Cost of Design

    Due to inability to leverage resources and IP across your design chain

Our publishing platform, which is based upon DesignSync, saves us two weeks of NPI cycle time on average, which in our business is substantial. We can load design workspaces in minutes that without DesignSync would take hours. While this was important with smaller projects, it is now critical for our larger ones.

Avery De Marr PLM Systems IT Manager, FreeScale Semiconductor

Explore the power of collaborative design & analysis

ENOVIA Pinpoint videos

Facilitate complex semiconductor projects with ENOVIA Pinpoint

For locally distributed engineering groups working on large ASIC and SoC projects, efficient collaboration has become increasingly more difficult.

Learn how ENOVIA Pinpoint helps keeping design projects on track by aggregating large amounts of data from different design and analysis tools, fostering analysis, metric tracking and team collaboration.

Click below to watch the overview video and 3 x 5-minute videos.

>> Watch the ENOVIA Pinpoint videos