Enterprise IP Management in the Semiconductor Industry

Operational Challenges Faced by the Semiconductor Industry

The reuse of IP blocks is a strategy with a proven ability to shorten design cycle times, reduce risks from quality issues, and minimize exposure to IP-related litigation.

It is also a strategy that has never been more important than today. Recent industry changes are increasing design and process complexity, while development costs continue to mount, margins shrink, and competition intensifies.

These changes make enterprise IP management a necessity for capturing and holding market share and achieving desirable returns on investments.

Key operational challenges faced by the semiconductor industry
Source: PwC analysis; "PwC 2014 M&A Integration Survey: Looking beyond the here and now."

 

Increasing Complexity

As forces such as the Internet of Things (IoT) drive the demand for broader functionality, the use of interchangeable IP blocks to address design complexity continues to rise.

Managing growing internal and external IP, however, is becoming more challenging as semiconductor companies seek to address technical and market challenges through mergers, acquisitions and cross-value chain ecosystem partnerships.

200+

Average IP Blocks
per SoC

75%

IP Block Reuse

Growth in the Number of IP Blocks per Design
Growth in the Number of IP Blocks per Design

John Blyler's Whitepaper series on Addressing Competitive Challenges with Enterprise IP Management

Meeting ever-shorter development cycles at expected profit margins requires that semiconductor companies carefully manage all their resources, especially their IP, across below- and above-the-line product workflows. The companies who successfully manage their IP can gain a competitive edge by:  

  • Reducing time to market while delivering products that address new applications and support compelling end user experiences 
  • Reducing design and verification costs and more easily maintaining price competitiveness
  • Deriving greater, timelier value from partnerships, mergers and acquisitions
  • Protecting themselves from IP-related litigation risks while increasing revenue from their own IP

Reach the full potential of IP-driven design

Reaping the full benefit of IP reuse requires overcoming two primary IP management challenges: scaling and sharing. Read this white paper to discover how specially-designed tools and platforms can be used in early phase of engineering to:

  • Address scaling by shifting from file-based workflows to enterprise IP solutions that accelerate design workflows.
  • Meet sharing challenges by leveraging solutions that enable collaboration across all phases of IP management.
  • 70% savings in product design time with content reuse, as shown in current studies.
Early Phase
Early-Phase: Click to enlarge

Capture More Value from IP Assets

This white paper explores mid-phase semiconductor IP management issues such as security, sourcing, licensing and royalties. Download it to learn:

  • Why security concerns are growing, and why the use of hard and soft IP security tags has a mixed record of success. 
  • Why sourcing merits its own dedicated management effort apart from IP cataloging or governance operations.
  • What companies can do to realize the hidden value of large untapped stores of unlicensed IP. 
Capture More Value from IP Assets
Mid-Phase: Click to enlarge

 

 

IP-related lawsuits are increasingly being used for competitive advantage. Growing patent ‘troll’ activities are requiring firms to manage IP tightly and be able to defend against claims.

Mark Davis Principal at Deloitte Consulting, based in New York City

Platform-Based Design for Agility & Optimal IP Reuse

How can firms quickly create SoCs in response to consumer preferences without ‘redesigning the wheel’ each time? This white paper explores how companies can meet this challenge by:

  • Deploying a platform-based environment to provide the IP governance infrastructure needed to help designers reuse IP.
  • Using functional virtual prototypes (FVPs) to bridge the gap between EDA tool-based RTL design and SoC implementation.
  • Employing system virtual prototype (SVP) to incorporate SoC hardware and software in unified IP management processes.
Platform-Based Design for Agility & Optimal IP Reuse
Platform-Based Design: Click to enlarge