Defect Engineer ()
Defect Engineer tracks defects associated with IP blocks, assesses the impact of defects on blocks included in hierarchical designs, and tracks activity associated with fixing defects. It supports both Enterprise Development Administration and Hierarchical Defect Management.
Enterprise Development Administration for Multisite Design and Collaboration
While it is important that designers working in geographically dispersed design centers share exactly the same data, it is equally important that they share the same design environment. Design tools must be configured for use on a specific project, and it is important that not only are all designers using the same versions of design tools, but that the tools used at different design centers, or on individually running Windows machines, be configured exactly the same. In addition, since integrated circuit designs typically consist of massive amounts of computer data files, efficient sharing of read-only data is also a necessity.
Administration of the design environments of geographically dispersed design teams is greatly simplified by centralizing administration at the enterprise level. Development environments are configured and automatically pushed to design sites to create development instances. These consist of a set of designer workspaces and all the infrastructure necessary to support those workspaces, including a set of design tools configured for use on the specific development, and data caches for sharing of read-only data, both at the module and file levels. Defect Engineer connects the 3DEXPERIENCE® platform with geographically distributed DesignSync® servers, which are used as both data repository servers, and to manage development instances at dispersed design centers.
Hierarchical Defect Management
Hierarchical Defect Management provides a collaborative and secure environment for resolving product development issues and defects amongst geographically dispersed development teams working on complex hierarchical designs. As design data contributed by individual teams is integrated into higher-level designs, the impact of a defect found in a given IP dataset can be widespread and difficult to track and manage.
The structure of complex integrated circuit (IC) designs such as IP blocks and cell libraries are modeled in Defect Engineer as “products” and a design “hierarchy” is modeled by establishing relationships between products. Because design data for large chips or IP blocks is typically hierarchically arranged, a defect found in a lower level block or sub-system can affect many parent products. For example, a defect found in an ALU module could affect a CPU module in which it is instantiated, which in turn might be instantiated in multiple top level products around the world. A defect found in a standard cell library could have a massive and far-reaching impact, as the library may have been used to construct hundreds of IP blocks. It is not uncommon for companies to have hundreds, or even thousands, of IP data sets as well as a multitude of low level components such as cell libraries, data path compilers, etc. Tracking the existence of defects and managing the resolution of defects associated with all these data sets is a massive and complex challenge. The hierarchical defect tracking capability in Defect Engineer provides the infrastructure necessary to capture and track the data needed to answer these important questions:
- What products are affected by a defect?
- What defects are present in a given product?
In addition, Defect Engineer provides the capability to track the activities associated with fixing or resolving defects answering other important questions:
- Who will benefit if a defect is fixed?
- In what new product releases is a defect no longer present?