Connector for DesignSync DFII ()
Connector for DesignSync® DFII provides design data management for Cadence® data, in either CDBA (Cadence DataBase Access) or OpenAccess formats. It extends the design data management capabilities for Software and System-on-a-Chip Designer.
Connector for DesignSync DFII integrates Software and System on-a-Chip Designer with the Cadence DFII (Design Framework II) graphical integrated circuit (IC) design environment, also known as Virtuoso, recognizing and efficiently managing Cadence library design data. The Cadence DFII IC graphical design environment is modified with the addition of Software and System-on-a-Chip Designer menus and commands. Designers are able to perform Design Data Management (DDM) operations such as check-in, checkout, or tag without leaving the familiar Cadence graphical environment, and without having to manage the actual collections of files and directories on disk, which represent Cadence objects such as schematic diagrams.
EDA Data Awareness – Cadence Library Recognition
Data awareness is important because data created and modified by EDA (Electronic Design Automation) tools, such as a Cadence schematic diagram or physical layout, is typically not stored on disk as a single file. Rather, a design object such as a schematic diagram consists of a specific set of files. In order for a DDM system to maintain a version history of changes to the schematic diagram, this set of files must be managed as a group. The group of files is also referred to as a “co-managed” set, or “collection object.” These collection objects are stored in a larger directory structure called a “library.” A Cadence “library” consists of “cells,” and a cell may contain multiple “views,” which are models used for different purposes, such a schematic view, a layout view, etc.
Software and System-on-a-Chip Designer recognizes Cadence DFII libraries on disk so as not to confuse them with ordinary directories and files. Collection objects are managed transparently to the end user. So, when a user issues a command to checkout a version of a schematic diagram, the appropriate versions of each of the member files of the collection object are checked out automatically. The member files of the collection are each individually version controlled, and a mapping is maintained between the version of the design object and the versions of the member files which constitute the version of the object. Storage of data in the DDM repository is efficient because only member files of a collection which are modified in an edit operation are stored in the new version of the design object. And because the design object is managed as a “collection,” the tool prevents direct modification to individual member files, which can result in the corruption of the object as a whole.
The User Interface
With the Connector for DesignSync DFII, Cadence data recognition allows users to operate on familiar constructs such as libraries, cells, and views. Software and System-on-a-Chip Designer menus are included in the Cadence graphical environment and its commands appear in menus in the Cadence Library Manager tool. Commands are integrated in the Cadence environment using both the Cadence SKILL API, and the Generic Data Management (GDM) layer. Menus are added using the SKILL API, and AutoCheckout/AutoCheckin functionality is enabled through the GDM layer. Where appropriate, Synchronicity® commands are overlaid in Cadence menus in the Library Manager tool.
In addition to being able to operate on libraries, cell, and views, DDM operations may also be performed on a data “Category.” For example, if a standard cell library has been categorized by types such as “FlipFlops”, all the “FlipFlops” could be checked out for edit in a single operation.
A unique capability is also provided to perform data management operations based on the “hierarchy” of the design. Knowledge of a design is obtained by walking its instance hierarchy using Cadence SKILL functions. For example, a Cadence library may include ALU and MULTIPLIER design blocks. If the top level ALU schematic is fetched, one might issue the “Synchronicity > Tag > Hierarchy” command which would identify and tag each version of each instance of the lower level schematics. The level of hierarchical depth can be controlled. For example, one might want to tag the hierarchy of a standard cell design, yet not descend into the transistor level representations of the standard cells themselves. Once a hierarchy is tagged, it could be fetched into a new workspace. The result would be that one or more libraries could be fetched, with valid Cadence library structures created on disk, but the local libraries would only include the cells/views which constitute the ALU design hierarchy. This is an example of the capability to construct a workspace with a subset of the data contained Cadence libraries as stored in the DDM repository.
Some operations are more efficient if performed using Software and System-on-a-Chip Designer products rather than running the commands from within the Cadence environment. For example, when starting a new project, it is typical that multiple libraries are put under revision control. Due to the restriction within Cadence that one must select a library before performing any operations, checking in multiple libraries requires that each be checked in separately. If a project consists of 50 libraries, for example, this is a tedious operation at best. Using Software and System-on-a-Chip Designer products, all 50 libraries can be checked in by running a single command.